1. Field of the Invention
This invention relates to an improved serial interface. More particularly, it relates to the consolidation of a four signal serial interface to as few as two differential signals by using sigma-delta encoded data and by combining transmit data with a clock having at least twice the speed as the bit rate of the transmit data.
2. Background of Related Art
FIG. 8 shows a conventional four signal, differential, serial interface between two separate circuits 700 and 702. One of the circuits is typically exposed to voltages in excess of the power voltage, and therefore is referred to herein as a high voltage circuit 702. In some situations it is desirable to AC couple a clock signal in a serial interface so that a codec or other high voltage circuit 702 may be electrically isolated from the ground of a low voltage circuit 700. It would similarly be desirable to AC couple the transmit data signal 716, the receive data signal 718, and the frame sync signal 712. If all signals between the low voltage circuit 700 and the high voltage circuit 702 are AC coupled, then there is essentially no need for a connection to exist between the ground of the low voltage circuit 700 and the ground of the high voltage circuit 702.
Unfortunately, in practical situations, once the grounds between the low voltage circuit 700 and high voltage circuit 702 are broken, a large common mode voltage may exist between the ground potential of the low voltage circuit 700 and the ground potential of the high voltage circuit 702. This large common mode voltage may interfere with the AC coupled digital signals in the isolated high voltage circuit 702.
To avoid this problem, differential AC coupled signaling is conventionally implemented to reject the common mode voltage. However, e.g., for four serial signals between the low voltage circuit 700 and the high voltage circuit 702, differential AC coupling would require eight high voltage capacitors: two for the clock signal 710, two for the transmit data signal 716, two for the receive data signal 718, and two for the frame sync signal 712 (with respect to the low voltage circuit 700). Unfortunately, eight high voltage isolation capacitors generally require an excessive amount of space and are cost prohibitive.
An example of a serial interface is the CSP1034 multi-processor mode SIO interface. Five serial signals are needed to complete this interface. Each of the five differential signal pairs would have to be isolated with a pair of capacitors for voltage isolation, but this would require ten high voltage capacitors at each end.
It is important to reduce the number of communication lines necessary to interface between circuits, particularly where one of the circuits is subject to higher voltages, e.g., a codec, because of the relative cost and circuitry of the individual lines. Moreover, it is important that with a consolidation of communication lines, consideration be given to ensure that the data clock can be recovered at the receiving end with minimal jitter.
In accordance with the principles of the present invention, serial streams are consolidated to reduce space and cost requirements. In one aspect, the invention provides a system for transmitting a single information signal combining a data signal with a clock signal corresponding to the bit rate of the data signal. The system comprises a transmit data signal, and a multiplied clock signal corresponding to at least twice the bit rate of the transmit data signal. A combined clock/data signal is formed consisting of a logical combination of the transmit data signal and the multiplied clock signal, and is transmitted to a separate circuit.
The receiver system comprises a receiver to receive the combined clock/data signal, and an edge detector to detect edges in the combined clock/data signal. A phase locked loop locks on a signal from the edge detector. A gate derives the clock signal from the combined clock/data signal, and a divider divides the derived clock signal to provide a recovered clock signal corresponding to the original bit rate of the original data signal. A latch driven by the phase locked loop derives the data signal from the combined clock/data signal.